Figure 59 Mddr Clock Configuration; Figure 60 Mddr Clock Configuration - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Figure 59 • MDDR Clock Configuration
DDR_SMC_FIC_CLK drives the DDR_FIC slave interface and defines the frequency at which the FPGA
fabric subsystem connected to this interface is intended to run. DDR_SMC_FIC_CLK can be configured
as a ratio of MDDR_CLK (1, 2, 3, 4, 6, 8, 12, or 16) through the MSS_CCC configurator in Libero SoC, as
shown in the following image. The maximum frequency of DDR_SMC_CLK is 200 MHz.
Figure 60 • MDDR Clock Configuration
If the MDDR_CLK ratio to M3_CLK is a multiple of 3, DDR_SMC_FIC_CLK's ratio to MDDR_CLK must
also be a multiple of 3, and vice versa. The configurator issues an error if this requirement is not met.
This limitation is imposed by the internal implementation of the MSS CCC.
3.12.2.2.1 FIC_2 Configuration
This is required to initialize the MDDR registers (optional when initializing from MSS). Configure FIC_2
(peripheral initialization) block, as shown in the following image to expose the MDDR APB interface
(MDDR_APB_SLAVE interface) in Libero SmartDesign. Use the MDDR_APB_SLAVE interface to
connect with the APB master logic in the FPGA fabric.
Microsemi Proprietary UG0446 User Guide Revision 7.0 124