Performance; I/O Utilization; Table 2 Supported Memory (Ddr2, Ddr3 And Lpddr1) Configurations; Table 3 Ddr Speeds - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
• Data line MDDR_DQ_ECC[0] when data width is x8
Table 2 • Supported Memory (DDR2, DDR3 and LPDDR1) Configurations
Width
(in
Memory SECDED
Depth Width Mode)
128M or ×32 ×36
Less
×16 ×18
×8 ×9
256M ×32 ×36
×16 ×18
×8 ×9
512M ×32 ×36
×16 ×18
×8 ×9
1G ×32 ×36
×16 ×18
x8 ×9
3.3

Performance

The following table shows the maximum data rates supported by MDDR subsystem for supported
memory types.
For more Information, refer to the "DDR Memory Interface Characteristics" section in
FPGA and SmartFusion2 SoC FPGA Datasheet.
Table 3 • DDR Speeds
Memory Type
LPDDR1
DDR2
DDR3
3.4

I/O Utilization

The following table lists the I/O utilization for the SmartFusion2 and IGLOO2 devices corresponding to
supported bus widths. The remaining I/Os in Bank 0 can be used for general purposes.
Table 4 • I/O Utilization for SmartFusion2 and IGLOO2 Devices
M2S/M2GL005/010/025/060/0
MDDR Bus 90
Width M2S/M2GL150-FCV484
36-bit –
32-bit –
18-bit Bank0 (59 pins)
SmartFusion2 and IGLOO2 Devices
M2S/M2GL
005/010/025/060/090 M2S/M2GL 050
M2S/M2GL150- (FCS325,
FCV484 VF400, FG484)
– –
✔ ✔
✔
–
– –
✔ ✔
✔
–
– –
✔ ✔
✔
–
– –
✔ ✔
✔
–
M2S/M2GL 050
(FCS325, VF400,
FG484)
–
–
Bank0 (59 pins)
Microsemi Proprietary UG0446 User Guide Revision 7.0
M2S/M2GL 050
(FG896)
✔
✔
–
✔
✔
–
✔
✔
–
✔
✔
–
Maximum Data Rate (Mbps)
400 Mbps (200 MHz)
667 Mbps (333.33 MHz)
667 Mbps (333.33 MHz)
M2S/M2GL 050
(FG896)
Bank0 (85 pins)
Bank0 (76 pins)
Bank0 (59 pins)
M2S/M2GL150(FC1152)
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
DS0128: IGLOO2
M2S/M2GL 150
(FC1152)
Bank2 (85 pins)
Bank2 (76 pins)
Bank2 (59 pins)
7