Use Model 3: Accessing Mddr From Cortex-M3 Processor; Figure 69 Mddr With Dual Ahb Interface - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Figure 69 • MDDR with Dual AHB Interface
DDR
DDR
SDRAM
I/O
The steps for accessing the MDDR from one or two AHB masters in the FPGA fabric is the same as in
"Use Model 1: Accessing MDDR from FPGA Fabric Through the AXI Interface" section on page 126
except for the following:
11. The single AHB or two AHB interfaces must be selected in the MSS external memory configurator
instead of AXI master.
12. One or two AHB masters must be connected through CoreAHB's in the SmartDesign canvas.
3.12.5

Use Model 3: Accessing MDDR from Cortex-M3 Processor

The Cortex-M3 processor can access the DDR SDRAM connected to the MDDR subsystem through the
MSS DDR bridge, as shown in
System Builder"
processor:
MDDR
DDR
Transaction
PHY
Controller
Controller
MSS
Master
AHB-Lite
Slave 1
Slave n
FPGA Fabric
Figure 70, page 131.This use model follows the steps
for using MDDR.Use the following steps to access the MDDR from the Cortex-M3
Microsemi Proprietary UG0446 User Guide Revision 7.0
MSS DDR
AXI
Bridge
DDR_FIC
AHB-Lite
Slave 1
MSS
AHB
Masters
Master
Slave n
"Design Flow Using
130