Sysreg Configuration Register Summary; Table 26 Address Table For Register Interfaces; Table 27 Sysreg Configuration Register Summary - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
The following table lists the categories of registers and their offset addresses. The base address of the
MDDR subsystem registers is 0x40020800.
Table 26 • Address Table for Register Interfaces
Registers
DDR Controller Configuration Register
Reserved
DDR_FIC Configuration Register Summary
Reserved
3.11.1

SYSREG Configuration Register Summary

In addition to the specific MDDR subsystem registers, the registers listed in the following table also
control the behavior of the MDDR subsystem. These registers are located in the SYSREG section of the
user's guide and are listed here for convenience. Refer to the "System Register Block" in the
IGLOO2 High Performance Memory Subsystem User Guide
and associated bits.
Table 27 • SYSREG Configuration Register Summary
Register Name
MDDR_CR
MDDR_IO_CALIB_CR
HPMSDDR_PLL_STATUS_LOW_CR RW-P
HPMSDDR_PLL_STATUS_HIGH_CR RW-P
HPMSDDR_FACC1_CR
HPMSDDR_FACC2_CR
HPMSDDR_CLK_CALIB_STATUS
DDRB_CR
HPMSDDR_PLL_STATUS
MDDR_IO_CALIB_STATUS
HPMSDDR_CLK_CALIB_STATUS
SOFT_RESET_CR
Flash
Register Write
Type Protect
RW-P Register
RW-P Register
Register
Register
RW-P Field
RW-P Field
RW-P Register
RW-P Register
RO –
RO –
RO –
RW-P Bit
Microsemi Proprietary UG0446 User Guide Revision 7.0
Address Offset Space
0×000:0×1FC
0×200:0×3FC
0×400:0×4FC
0×500:0×7FC
for a detailed description of each register
Reset Source Description
PORESET_N MDDR Configuration register
PORESET_N MDDR I/O Calibration Control
register
CC_RESET_N Used to control the corresponding
configuration input of the MPLL.
CC_RESET_N Used to control the corresponding
configuration input of the MPLL
register
CC_RESET_N HPMS DDR Fabric Alignment Clock
Controller 1 Configuration register
CC_RESET_N HPMS DDR Fabric Alignment Clock
Controller 2 Configuration register
SYSRESET_N Used to start an FPGA fabric
calibration test circuit.
SYSRESET_N HPMS DDR bridge configuration
register
– HPMS DDR PLL Status register
PORESET_N DDR I/O Calibration Status register
SYSRESET_N HPMS DDR Clock Calibration Status
register
SYSRESET_N Soft reset control register
UG0448:
62