Soft Memory Controller Fabric Interface Controller
Table 166 • SMC_FIC 64-bit AXI Port List (continued)
Signal
MDDR_SMC_AXI_M_BREADY
MDDR_SMC_AXI_M_AWVALID
MDDR_SMC_AXI_M_ARVALID
MDDR_SMC_AXI_M_RREADY
MDDR_SMC_AXI_M_AWREADY
MDDR_SMC_AXI_M_WREADY
MDDR_SMC_AXI_M_BVALID
MDDR_SMC_AXI_M_ARREADY
MDDR_SMC_AXI_M_RLAST
MDDR_SMC_AXI_M_RVALID
Direction Polarity Description
Output
High
Output
High
Output
High
Output
High
Input
High
Input
High
Input
High
Input
High
Input
High
Input
High
Microsemi Proprietary UG0446 User Guide Revision 7.0
Indicates whether or not the master can accept the
response information.
1: Master ready
0: Master not ready
Indicates whether or not valid write address and control
information are available.
1: Address and control information available
0: Address and control information not available
Indicates whether or not valid read address and control
information are available.
1: Address and control information valid
0: Address and control information not valid
Indicates whether or not the master can accept the
read data and response information.
1: Master ready
0: Master not ready
Indicates that the slave is ready to accept an address
and associated control signals.
1: Slave ready
0: Slave not ready
Indicates whether or not the slave can accept the write
data.
1: Slave ready
0: Slave not ready
Indicates whether or not a valid write response is
available.
1: Write response available
0: Write response not available.
Indicates whether or not the slave is ready to accept an
address and associated control signals.
1: Slave ready
0: Slave not ready
Indicates the last transfer in a read burst.
Indicates whether or not the required read data is
available and the read transfer can complete.
1: Read data available
0: Read data not available
221
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