Timing Optimization Technique For Axi; Figure 40 Ddr Controller Command Sequence For Axi Incr-16 Read Transaction; Table 24 Number Of Cycles For Axi/Ahb Transactions To Mddr - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Figure 40 • DDR Controller Command Sequence for AXI INCR-16 Read Transaction
MDDR_CAS_N
MDDR_CKE
MDDR_CLK
MDDR_CLK_N
MDDR_CS_N
MDDR_ODT
MDDR_RAS_N
MDDR_RESET_N
MDDR_WE_N
MDDR_ADDR
MDDR_BA
MDDR_DM_RDQS
MDDR_DQS
MDDR_DQS_N
MDDR_DQ
MDDR_DQS_TMATCH_0_IN
MDDR_DQS_TMATCH_0_OUT
mddr_dqs_tmatch_0_out
The following table summarizes the number of cycles to complete the AXI/AHB transactions to MDDR.
Table 24 • Number of Cycles for AXI/AHB Transactions to MDDR
Transaction Type
AXI Single
AXI INCR16 Burst
3.8

Timing Optimization Technique for AXI

The AXI mode of the MDDR or FDDR provides the highest throughput interface to the external memory
device. The best interface ratio for clocking is 2:1 ratio which keeps the fabric clock and fabric interface
running at the same rate as the external memory device. For these types of interfaces the following
technique provides an optimization method for timing closure when using the 2:1 interface. Timing
closure can be achieved by Timing Optimization Technique when the timing closure is not met with the
design.
The optimization method can reside between an existing AXI master and the DDR_FIC AXI slave
interface and no changes are required to the AXI master design. The following illustration shows a
diagram of the technique, which uses a negative edge register on the VALID lines.
0000
0 0
Read transac on to
DDR Memory ini ated
Write Cycles
4
31
Microsemi Proprietary UG0446 User Guide Revision 7.0
0008 0010 0018 0020 0028 0030
0 0 0 0 0 0 0 0 0 0
Read Cycles
19
49
0038
0 0 0 0 0 0
55