Table 47 Ddrc_Dram_Rd_Wr_Latency_Cr - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Table 46 • DDRC_DRAM_BANK_TIMING_PARAM_CR
[11:6] REG_DDRC_T_RC
[5:0] REG_DDRC_T_FAW
Table 47 • DDRC_DRAM_RD_WR_LATENCY_CR
Bit
Number Name
[31:10] Reserved
[9:5] REG_DDRC_WRITE_LATENCY 0×0
[4:0] REG_DDRC_READ_LATENCY
Table 48 • DDRC_DRAM_RD_WR_PRE_CR
Bit
Number Name
[31:10] Reserved
[9:5] REG_DDRC_WR2PRE 0×0
[4:0] REG_DDRC_RD2PRE
Table 49 • DDRC_DRAM_MR_TIMING_PARAM_CR
Bit
Number Name
0×0 t : Minimum time between activates to same bank (specification: 65 ns
RC
for DDR2-400 and smaller for faster parts). Unit: clocks.
0×0 t : Valid only in burst-of-8 mode.
FAW
At most 4 banks must be activated in a rolling window of tFAW cycles.
Unit: clocks
Reset
Value Description
0×0 Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
Number of clocks between the write command to write data
enable PHY.
0×0 Time from read command to read data on DRAM interface.
Unit: clocks
This signal is present for designs supporting LPDDR1 DRAM
only. It is used to calculate when the DRAM clock may be
stopped.
Reset
Value Description
0×0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Minimum time between write and precharge to same bank
(specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14
clocks @ 400 MHz and less for lower frequencies).
Unit: Clocks
where:
WL = Write latency
BL = Burst length. This must match the value programmed in the BL bit
of the mode register to the DRAM.
t = Write recovery time. This comes directly from the DRAM specs.
WR
0×0 t – Minimum time from read to precharge of same bank
RTP
(specification: tRTP for BL = 4 and tRTP + 2 for BL = 8. tRTP = 7.5 ns).
Unit: clocks.
Reset
Value Description
Microsemi Proprietary UG0446 User Guide Revision 7.0 76