Figure 118 Fic_2 Configuration; Figure 119 Mss Ccc Configuration - Microchip Technology Microsemi SmartFusion2 User Manual

Fabric DDR Subsystem
Figure 118 • FIC_2 Configuration
4. Configure MSSCCC for the FIC_0 clock, as shown in the following image. The FIC_0 clock is
configured to 111 MHz.
Figure 119 • MSS CCC Configuration
5. Instantiate the DDR Memory Controller macro in the SmartDesign canvas.
6. Configure the FDDR and select the dual AHB interface, as shown in the following image. In this
example, the design is created to access DDR3 memory with a 32-bit data width. The FDDR clock is
configured to 333 MHz and DDR_FIC is configured to 111 MHz.
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