Functional Description; Architecture Overview; Table 163 Smartfusion2 And Igloo2 Fpga Ddr Bridge Interface - Microchip Technology Microsemi SmartFusion2 User Manual

DDR Bridge
masters are fixed, as shown in the following table. The DDR bridges in the MDDR and FDDR
subsystems support only two AHB interfaces out of four and these can be used for user implemented
AHB masters.
Table 163 • SmartFusion2 and IGLOO2 FPGA DDR Bridge Interface
DDR Bridge
Sub- AHB Interface 0
System Read Only
HPMS Not available—
MSS Cache Controller
IDC
MDDR Not available
FDDR Not available
Note: If the AXI bus is selected as the interface between the FPGA fabric and the MDDR/ FDDR subsystem,
the DDR bridge in these subsystems is not used.
5.1

Functional Description

This section provides the detailed description of the DDR Bridge, which contains the following sections:
•

Architecture Overview

• Details of Operation
5.1.1 Architecture Overview
The DDR bridge consists of two main components: read and write combining buffers (WCB), and an
arbiter, as shown in the following illustration. The DDR bridge buffers AHB write transactions into write
combining buffers before bursting out to external DDR memory. It also includes read buffers for AHB
masters to efficiently read data from the external DDR memory. All buffers within the DDR bridge are
implemented with latches and hence are not subject to single event upsets (SEUs). The external DDR
memory regions can be configured to be non-bufferable. If a master interface requests a write or read to
a non-bufferable region, the DDR bridge is essentially bypassed. The size of the non-bufferable address
space can also be configured.
AHB Interface 1 AHB Interface 2
R/W R/W
Not available— AHB bus matrix HPDMA
Cache Controller AHB bus matrix HPDMA
DS
Not available AHB master
interface 0
Not available AHB master
interface 0
Microsemi Proprietary UG0446 User Guide Revision 7.0
AHB Interface 3
R/W AXI Interface
MDDR
subsystem
MDDR
subsystem
AHB master MDDR
interface 1 subsystem
AHB master FDDR
interface 1 subsystem
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