Figure 53 Mddr Clock Configuration - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Figure 53 • MDDR Clock Configuration
DDR_FIC_CLK drives the DDR_FIC slave interface and defines the frequency at which the FPGA fabric
subsystem connected to this interface is intended to run. DDR_FIC_CLK can be configured as a ratio of
MDDR_CLK (1, 2, 3, 4, 6, 8, 12, or 16) using the Clocks configurator. The maximum frequency of
DDR_FIC_CLK is 200 MHz. The following image shows the DDR_FIC_CLK configuration.
If the MDDR_CLK ratio to M3_CLK is a multiple of 3, DDR_SMC_FIC_CLK's ratio to MDDR_CLK must
also be a multiple of 3, and vice versa. The configurator issues an error if this requirement is not met.
This limitation is imposed by the internal implementation of the MSS CCC.
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