Microchip Technology Microsemi SmartFusion2 User Manual page 234

Soft Memory Controller Fabric Interface Controller
Table 166 • SMC_FIC 64-bit AXI Port List (continued)
Signal
MDDR_SMC_AXI_M_ARLEN[3:0]
MDDR_SMC_AXI_M_ARSIZE[1:0]
MDDR_SMC_AXI_M_ARBURST[1:0]
MDDR_SMC_AXI_M_AWADDR[31:0] Output
MDDR_SMC_AXI_M_AWSIZE[1:0]
MDDR_SMC_AXI_M_AWLOCK[1:0]
Direction Polarity Description
Output
Output
Output
Output
Output
Microsemi Proprietary UG0446 User Guide Revision 7.0
Indicates burst length. The burst length gives the exact
number of transfers in a burst.
0000: 1
0001: 2
0010: 3
0011: 4
0100: 5
0101: 6
0110: 7
0111: 8
1000: 9
1001: 10
1010: 11
1011: 12
1100: 13
1101: 14
1110: 15
1111: 16
Indicates the maximum number of data bytes to
transfer in each data transfer, within a burst.
00: 1
01: 2
10: 4
11: 8
Indicates burst type. The burst type, coupled with the
size information, provides details on how the address
for each transfer within the burst is calculated.
00: FIXED – Fixed-address burst, FIFO type
01: INCR – Incrementing-address burst, normal
sequential memory
10: WRAP – Incrementing-address burst that wraps to
a lower address at the wrap boundary
11: Reserved
Indicates write address. The write address bus gives
the address of the first transfer in a write burst
transaction.
Indicates the maximum number of data bytes to
transfer in each data transfer, within a burst.
00: 1
01: 2
10: 4
11: 8
Indicates lock type. This signal provides additional
information about the atomic characteristics of the write
transfer.
00: Normal access
01: Exclusive access
10: Locked access
11: Reserved
223