Port List; Table 5 Mddr Subsystem Interface Signals - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
3.5.2

Port List

Table 5 • MDDR Subsystem Interface Signals
Signal Name
APB_S_PCLK
APB_S_PRESET_N
MDDR_DDR_CORE_RESET_N
MDDR_DDR_AXI_S_RMW
HPMS_DDR_FIC_SUBSYSTEM_CLK
or,
MSS_DDR_FIC_SUBSYSTEM_CLK
HPMS_DDR_FIC_SUBSYSTEM_LOCK
or,
MSS_DDR_FIC_SUBSYSTEM_LOCK
Bus Interfaces
1
AXI_SLAVE
2
AHB0_SLAVE
3
AHB1_SLAVE
APB_SLAVE
DRAM Interface
MDDR_CAS_N
MDDR_CKE
MDDR_CLK
MDDR_CLK_N
MDDR_CS_N
MDDR_ODT
MDDR_RAS_N
MDDR_ RESET_N
MDDR_WE_N
Type Polarity
In –
In Low
In Low
In High
Out –
Out –
Bus –
Bus –
Bus –
Bus –
Out Low
Out High
Out –
Out –
Out Low
Out High
Out Low
Out Low
Out Low
Microsemi Proprietary UG0446 User Guide Revision 7.0
Description
APB clock. This clock drives all the registers of the
APB interface.
APB reset signal. This is an active low signal. This
drives the APB interface and is used to generate the
soft reset for the DDR controller as well.
Global reset. This resets the
DDR_FIC/DDRC/PHY/DDRAXI logic.
AXI mode only Indicates whether all bytes of a
64-bit lane are valid for all beats of an AXI transfer.
0: Indicates that all bytes in all beats are valid in the
burst and the controller should default to write
commands.
1: Indicates that some bytes are invalid and the
controller should default to RMW commands. This
is classed as an AXI write address channel
sideband signal and is valid with the AWVALID
signal.
This output clock is derived from the MDDR_CLK
and is based on the DDR_FIC divider ratio. This is
the clock that should be used for the AXI or AHB
slave interfaces to move data in and out of the
MDDR.
This indicates the lock from FCCC which generates
HPMS_DDR_FIC_SUBSYSTEM_CLK for IGLOO2
and MSS_DDR_FIC_SUBSYSTEM_LOCK in
SmartFusion2.
AXI slave interface 1.0 bus
AHB0 slave interface 3.0 bus
AHB1 slave interface 3.0 bus
APB slave interface 3.0 bus
DRAM CASN
DRAM CKE
DRAM single-ended clock – for differential pads
DRAM single-ended clock – for differential pads
DRAM CSN
DRAM ODT.
0: Termination Off
1: Termination On
DRAM RASN
DRAM reset for DDR3
DRAM WEN
9