Accessing Fddr From Fpga Fabric Through The Axi Interface; Figure 88 Fddr Clock Configuration; Figure 89 I/O Editor Window - Microchip Technology Microsemi SmartFusion2 User Manual

Fabric DDR Subsystem
Figure 88 • FDDR Clock Configuration
4.7.1.1 I/O Configuration
In the I/O Editor window, configure the I/O settings such as ODT and drive strength. The following image
shows the I/O Editor window.
Figure 89 • I/O Editor Window
4.7.2

Accessing FDDR from FPGA Fabric through the AXI Interface

The AXI master in the FPGA fabric can access the DDR memory through the FDDR subsystem. The
following illustration shows the FDDR with the AXI interface. The FDDR registers are configured from the
FPGA fabric using the CoreConfigMaster IP through the CoreConfigP IP APB interface.
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