Figure 77 Ddr_Fic Block Diagram; Table 132 Fddr_Clk To Fpga Fabric Clock Ratios - Microchip Technology Microsemi SmartFusion2 User Manual

Fabric DDR Subsystem
In the event of loss of FPLL lock, even though its output is not exactly in phase lock with the reference,
the FPLL still generates a clock. User logic in the FPGA fabric can use the FPLL_LOCK signal to prevent
communication with the FDDR subsystem during this time.
4.6.3.2 DDR_FIC
The following illustration shows the DDR_FIC block diagram.
Figure 77 • DDR_FIC Block Diagram
64-Bit AXI / Single
32-Bit AHBL /
Dual 32-Bit AHBL
Slave Interface
16-Bit APB
Configuration Bus
Fabric masters can access the FDDR subsystem in the following ways:
• Single AXI-64 interface
• Single AHB-32 interface
• Dual AHB-32 bit interfaces
If the AXI-64 interface is selected, the DDR_FIC acts as an AXI to AXI synchronous bridge and also
supports locked transactions. During locked transactions a user configurable 20-bit down counter keeps
track of the duration of the locked transfer. If the transfer is not completed before the down counter
reaches zero, a single clock cycle pulse interrupt is generated to the fabric interface.
If single or dual AHB-32 interfaces are selected, the DDR_FIC converts the single or dual 32-bit AHBL
master transactions from the FPGA fabric to 64-bit AXI transactions. The DDR bridge, which is
embedded as part of the DDR_FIC, is enabled in this case. The DDR bridge has an arbiter that uses a
round robin priority scheme on read and write requests from the two AHB masters. Refer to the
Bridge" chapter on page 207
The DDR_FIC input interface is clocked by the FPGA fabric clock and the AXI transaction controller is
clocked by FDDR_CLK from the FDDR clock controller. Clock ratios between FDDR_CLK and DDR_FIC
clock can vary. Supported ratios are shown in the following table. Clock ratios can be configured through
Libero System-on-Chip (SoC) software or through the FDDR_FACC_DIVISOR_RATIO register.
Table 132 • FDDR_CLK to FPGA Fabric Clock Ratios
DIVISOR_A[1:0]
00
00
00
00
00
01
01
01
01
11
AHB
DDR Bridge
AHB
MUX
AXI AXI-AXI
Synchronous
Configuration
Registers
for a detailed description.
DDR_FIC DIVISOR[2:0]
000
001
010
100
101
000
001
010
100
000
Microsemi ProprietaryUG0446 User Guide Revision 7.0
AXI
MUX
AXI
Bridge
FDDR_CLK: FPGA FABRIC Clock Ratio
1:1
2:1
4:1
8:1
16:1
2:1
4:1
8:1
16:1
3:1
AXI Transaction
Controller
"DDR
148