Figure 64 Mss External Memory Configuration; Figure 65 Configuring Fic_2; Figure 66 Mddr Clock Configuration - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Figure 64 • MSS External Memory Configuration
4. Configure FIC_2, as shown in the following image, to enable the MDDR subsystem APB interface
for configuring the MDDR registers using APB master in the FPGA fabric.
Figure 65 • Configuring FIC_2
5. Configure the MSS_CCC for MDDR_CLK and DDR_SMC_FIC_CLK. In the following image, the
MDDR clock is configured to 333 MHz and M3_CLK is configured to 111 MHz.
Figure 66 • MDDR Clock Configuration
6. Instantiate the clock resources (FCCC and chip oscillators) in the SmartDesign canvas and
configure, as required.
7. Instantiate user AXI master logic in the SmartDesign canvas to access the MDDR through the AXI
interface. Make sure that the AXI master logic accesses the MDDR after configuring the MDDR
registers from the APB master. The AXI master clock should be same as DDR_SMC_FIC_CLK.
8. Instantiate user APB master logic in the SmartDesign canvas to configure the MDDR registers
through the APB interface. The APB master logic should initialize the registers after the MSS comes
out of reset. The APB clock must be connected to FIC_2_APB_M_PCLK.
9. Connect the AXI master and APB master to the MSS component through CoreAXI and CoreAPB or
use the auto connect option in SmartDesign.
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