Table 11 Secded Dq Lines At Ddr - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
The SECDED bits are interlaced with the data bits, as listed in the following table.
Table 11 • SECDED DQ Lines at DDR
SECDED Data Pins
M2S/M2GL005/010/025
/060/090
Mode M2S/M2GL150-FCV484
Full bus width —
Half bus width MDDR_DQ_ECC[1:0]
Quarter bus width MDDR_DQ_ECC[0]
When the controller detects a correctable SECDED error, it does the following:
1. Generates an interrupt signal which can be monitored by reading the interrupt status register,
DDRC_ECC_INT_SR. The ECCINT interrupt is mapped to the group0 interrupt
signalMSS_INT_M2F[12] in SmartFusion2 or HPMS_INT_M2F[12] in IGLOO2 of the fabric interface
interrupt controller (FIIC).
2. Sends the corrected data to the read requested MSS/HPMS FPGA fabric master as part of the read
data.
3. Sends the SECDED error information to the
4. Performs a read-modify-write operation to correct the data present in the DRAM.
When the controller detects an uncorrectable error, it does the following:
1. Generates an interrupt signal which can be monitored by reading the interrupt status register,
DDRC_ECC_INT_SR. The ECCINT interrupt is mapped to the group0 interrupt signal
MSS_INT_M2F[12] in SmartFusion2 or HPMS_INT_M2F[12] in IGLOO2 of the FIIC.
2. Sends the data with error to the read requested MSS/HPMS FPGA fabric master as part of the read
data.
3. Sends the SECDED error information to the
The following
DDR SDRAM.
1. DDRC_LUE_ADDRESS_1_SR and DDRC_LUE_ADDRESS_2_SR give the row/bank/column
information of the SECDED unrecoverable error.
2. DDRC_LCE_ADDRESS_1_SR and DDRC_LCE_ADDRESS_2_SR give the row/bank/column
information of the SECDED error correction.
3. DDRC_LCB_NUMBER_SR indicates the location of the bit that caused the single-bit error in the
SECDED case (encoded value).
4. DDRC_ECC_INT_SR indicates whether the SECDED interrupt is because of a single-bit error or
double-bit error. The interrupt can be cleared by writing zeros to DDRC_ECC_INT_CLR_REG.
3.5.4.3.5 Power Saving Modes
The DDR controller can operate DDR memories in three power saving modes:
Precharge Power-Down (DDR2, DDR3, LPDDR1)
• If power-down is enabled in the System Builder MDDR configuration or
REG_DDRC_POWERDOWN_EN
precharge power-down mode when the period specified by the power down entry time or
REG_DDRC_POWERDOWN_TO_X32
issuing refreshes).
• The controller automatically performs the precharge power-down exit on any of the following
conditions:
• A refresh cycle is required to any rank in the system.
• The controller receives a new request from the core logic.
• REG_DDRC_POWERDOWN_EN is set to 0.
Self Refresh (DDR2, DDR3, LPDDR1)
M2S/M2GL 050
(FCS325, VF400,
FG484)
—
MDDR_DQ_ECC[1:0] MDDR_DQ_ECC[1:0]
—
SECDED Registers can be monitored for identifying the exact location of an error in the
= 1, the DDR controller automatically keeps DDR memory in
Microsemi Proprietary UG0446 User Guide Revision 7.0
M2S/M2GL 050
(FG896)
MDDR_DQ_ECC[3:0]
—
DDRC_LCE_SYNDROME_1_SR
DDRC_LUE_SYNDROME_1_SR
register has passed, while the controller is idle (except for
M2S/M2GL 150
(FC1152)
MDDR_DQ_ECC[3:0]
MDDR_DQ_ECC[1:0]
MDDR_DQ_ECC[0]
register.
register.
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