Table 15 Dynamically-Enforced Bank Constraints; Table 16 Dynamic Dram Global Constraints - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
3.5.5.5.1 Dynamic DRAM Rank Constraints
The timing constraints that affect the transactions to a rank are listed in the following table. The control bit
field must be configured as per the DDR memory vendor specification.
Table 15 • Dynamically-Enforced Bank Constraints
Timing Constraints of DDR
Memory
Nominal refresh cycle time
(t ) or t )
RFC(nom REFI
Minimum refresh cycle time
t
RFC(min)
RAS-to-rAS delay (t )
RRD
RAS-to-CAS delay (t )
CCD
Four active window (t )
FAW
3.5.5.5.2 Dynamic DRAM Global Constraints
The timing constraints that affect global transactions are listed in the following table. The control bit field
must be configured as per the DDR memory vendor specification.
Table 16 • Dynamic DRAM Global Constraints
Timing Constraint
Read-to-write turnaround time
(t )
RTW
Write-to-read turnaround time
(t )
RTR
Write latency
The DDR memories require delays after initializing the mode registers. The following registers must be
configured for the delay requirements for the DDR memories. The DDR controller uses these delay
values while initializing the DDR memories.
• DDRC_CKE_RSTN_CYCLES_1_CR
• DDRC_ CKE_RSTN_CYCLES_2_CR
3.5.5.6 Address Mapping
The DDR controller maps linear request addresses to DDR memory addresses by selecting the source
bit that maps to each and every applicable DDR memory address bit.
Each DDR memory address bit has an associated register vector to determine its source. The source
address bit number is determined by adding the internal base of a given register to the programmed
value for that register, as described in
Control Bit
REG_DDRC_T_RFC_NOM_X32
REG_DDRC_T_RFC_MIN
REG_DDRC_T_RRD
REG_DDRC_T_CCD
REG_DDRC_T_FAW
Control Bit
REG_DDRC_RD2WR
REG_DDRC_WR2RD
REG_DDRC_WRITE_LATENCY
(recommended value is 0x4242)
(recommended value is 0x8)
EQ 1.
Microsemi Proprietary UG0446 User Guide Revision 7.0
Description
Average time between refreshes for a given rank.
The actual time between any two refresh
commands may be larger or smaller than this; this
represents the maximum time allowed between
refresh commands to a given rank when averaged
over a large period of time.
Minimum time from refresh to refresh or activate.
Minimum time between activates from bank A to
bank B.
Minimum time between two reads or two writes
(from bank A to bank B).
Sliding time window in which a maximum of:
4 bank activates are allowed in an 8-bank design.
In a 4-bank design, set this register to 0x1.
Description
Minimum time to allow between issuing any
Read command and issuing any WRITE
command
Minimum time to allow between issuing any Write
command and issuing any Read command
Time after a Write command that write data
should be driven to DRAM.
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