Figure 35 Axi Single Read Transaction And Corresponding Ddr Controller Commands; Figure 36 Axi Incr16 Write Transaction And Corresponding Ddr Controller Commands - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Figure 35 • AXI Single Read Transaction and Corresponding DDR Controller Commands
MDDR_CLK_N
MDDR_CS_N
MDDR_ODT
MDDR_RAS_N
MDDR_RESET_N
MDDR_WE_N
0000
MDDR_ADDR
1
MDDR_BA
MDDR_DM_RDQS
MDDR_DQS
MDDR_DQS_N
MDDR_DQ
MDDR_DQS_TMATCH_0_IN
MDDR_DQS_TMATCH_0_OUT
DDR read controls
CLK
0
ARID
00000000
ARADDR
ARLEN 0
ARSIZE 3
0
ARLOCK
1
ARBURST
ARVALID
ARREADY
0
RID
RDATA
RVALID
RLAST
RREADY
0
RRESP
0 1 2
CLK_CNT
Figure 36 • AXI INCR16 Write Transaction and Corresponding DDR Controller Commands
MDDR_CAS_N
MDDR_CKE
MDDR_CLK
MDDR_CLK_N
MDDR_CS_N
MDDR_ODT
MDDR_RAS_N
MDDR_RESET_N
MDDR_WE_N
0400
MDDR_ADDR
1
MDDR_BA
MDDR_DM_RDQS
MDDR_DQS
MDDR_DQS_N
MDDR_DQ
MDDR_DQS_TMATCH_0_IN
MDDR_DQS_TMATCH_0_OUT
mddr_dqs_tmatch_0_out
DDR write controls
CLK
0
0
AWID
0
AWADDR
f
AWLEN
3
AWSIZE
0
AWLOCK
1
AWBURST
AWVALID
AWREADY
WID
WSTRB
WLAST
WVALID
WDATA
WREADY
BID
RESP
BVALID
BREADY
0 1
0
Read transac on to DDR
Memory ini ated by MDDR
5 6 7
3 4
Refer
0
ff
1 2 7
3 4 5 6 8 9 10 11
18 19 20
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Microsemi Proprietary UG0446 User Guide Revision 7.0
0 3
3 0
1
9
8 10 11 12 13
ss
ss
ss
ss
ss
0000
Write transac on to 0
DDR Memory ini ated
ss
ss
ss
ss
Figure 1-34 on page 55
ss
ss
ss
ss
ss
ss
ss
ss
12 13 14 15 16
ss
0
ss
CLK Cycles for comple ng
0
transac on
ss
Refer
ss
25 26 27 28 29 30 31 32 33 54 55 56 57
21 22 23 24
0 3 0 3 0 3 0
3 0 3 0 3 0 3
0 1 0
1
CLK Cycles for comple ng
transac on
16 17 18 19
14 15
0008 0010 0018 0020 0028 0030 0038
0
Figure 1-33 on page 55
65 66 67 68 69 70 71 72
58 59 60 61 62 63 64 73 74 75 76
20
77 78 79 8
53