Table 150 Pll_Delay_Line_Sel - Microchip Technology Microsemi SmartFusion2 User Manual

Fabric DDR Subsystem
Table 150 • PLL_DELAY_LINE_SEL
Bit
Number Name
[31:4] Reserved
[3:2] PLL_FB_DEL_SEL
[1:0] PLL_REF_DEL_SEL
Table 151 • FDDR_SOFT_RESET
Bit
Number Name
[31:2] Reserved
1 FDDR_DDR_FIC_SOFTRESET
0 FDDR_CTLR_SOFTRESET
Table 152 • FDDR_IO_CALIB
Bit
Number Name
[31:15] Reserved
14 CALIB_TRIM
Reset
Value
0×0
0×0
0×0
Reset
Value
0×0
0×1
0×1
Reset
Value
0×0
0×0
Microsemi ProprietaryUG0446 User Guide Revision 7.0
Description
Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a
read-modify-write operation.
Selects the delay values that are added to the FPLL
feedback clock before being output to the FPLL.
00: No buffer delay
01: One buffer delay
10: Two buffers delay
11: Three buffers delay
Selects the delay values that are added to the FPLL
reference clock before being output to the FPLL.
00: No buffer delay
01: One buffer delay
10: Two buffers delay
11: Three buffers delay
Description
Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a
read-modify-write operation.
When 1, holds the DDR_FIC (AXI/AHB) interface
controller in reset.
When 1, holds the FDDR subsystem in reset.
Description
Software should not rely on the value of a reserved
bit. To provide compatibility with future products,
the value of a reserved bit should be preserved
across a read-modify-write operation.
Indicates override of the calibration value from the
pc code / programmed code values in the DDRIO
calibration block.
181