Table 112 Ddr_Fic_Num_Ahb_Masters_Cr - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Table 111 • DDR_FIC_ERR_INT_ENABLE
1 SYR_SW_WR_ERR
0 SYR_HPD_WR_ERR
Table 112 • DDR_FIC_NUM_AHB_MASTERS_CR
Bit
Number Name
[31:5] Reserved
4 CFG_NUM_AHB_MASTERS 0×0
[3:0] Reserved
Table 113 • DDR_FIC_HPB_ERR_ADDR_1_SR
Bit
Number Name
[31:16] Reserved
[15:0] DDR_FIC_M1_ERR_ADD
0×0 Status bit.
Goes High when error response is received for bufferable write
request.
Goes Low when processor serves interrupt and makes clear
bit for AHBL master1.
0×0 Status bit.
Goes High when error response is received for bufferable write
request.
Goes Low when processor serves the interrupt.
Reset
Value Description
0×0 Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
Defines whether one or two AHBL 32-bit masters are
implemented in the fabric.
0: One 32-bit AHB master implemented in fabric
1: Two 32-bit AHB masters implemented in fabric
0×0 Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
Reset
Value Description
0×0 Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
0×0 32 bits are split into two registers.
[15:0] bits of DDR_FIC_M1_ERR_ADD
Tag of write buffer for which error response is received is placed
in this register. The following values are updated in this register
as per buffer size:
Buffer size
16 bytes: 28 bit TAG value is loaded to [31:4] and 0000 to [3:0]
32 bytes: upper 27 bits of TAG is loaded to [31:5] and 00000 to
[4:0]
Microsemi Proprietary UG0446 User Guide Revision 7.0 108