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MDDR Subsystem
3.7
Timing Diagrams
This section shows the operation of the DDR controller with AXI interface with Timing diagrams. The
DDR3 16-bit micron memory model is used to perform the read and write transactions from MDDR
Fabric Interface (DDR_FIC). The AXI/AHB clock is configured for 166 MHz and MDDR clock is
configured for 332 MHz, that is, FIC clock to MDDR clock ratio is 1:2.
Figure 33 • AXI Single Write Transaction and Corresponding DDR Controller Commands
MDDR_DQS_TMATCH_0_IN
MDDR_DQS_TMATCH_0_OUT
DDR write controls
Figure 34 • DDR Controller Command Sequence for Single AXI Write Transaction
MDDR_CAS_N
MDDR_CKE
MDDR_CLK
MDDR_CLK_N
MDDR_CS_N
MDDR_ODT
MDDR_RAS_N
MDDR_RESET_N
MDDR_WE_N
MDDR_ADDR
0400
MDDR_BA
1
Write transaction to DDR
Memory initiated by MDDR
MDDR_DM_RDQS
MDDR_DQS
MDDR_DQS_N
MDDR_DQ
CLK
0
AWID
0
AWADDR
AWLEN
0
AWSIZE
3
0
AWLOCK
1
AWBURST
AWVALID
AWREADY
0
WID
ff
WSTRB
WLAST
WVALID
1
WDATA
WREADY
0
BID
CLK Cycles for completing
0
BRESP
AXI transaction
BVALID
BREADY
0
CLK_COUNT
1
2
3
4
5
6
7
8
MDDR_CAS_N
MDDR_CKE
MDDR_CLK
MDDR_CLK_N
MDDR_CS_N
MDDR_ODT
MDDR_RAS_N
MDDR_RESET_N
MDDR_WE_N
MDDR_ADDR
MDDR_BA
MDDR_DM_RDQS
MDDR_DQS
MDDR_DQS_N
MDDR_DQ
MDDR_DQS_TMATCH_0_IN
MDDR_DQS_TMATCH_0_OUT
Microsemi Proprietary UG0446 User Guide Revision 7.0
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Figure 1-34 on Page 60
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