Table 50 Ddrc_Dram_Ras_Timing_Cr - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Table 49 • DDRC_DRAM_MR_TIMING_PARAM_CR
[31:13] Reserved
[12:3] REG_DDRC_T_MOD
[2:0] REG_DDRC_T_MRD
Table 50 • DDRC_DRAM_RAS_TIMING_CR
Bit
Number Name
[31:11] Reserved
[10:5] REG_DDRC_T_RAS_MAX 0×0
[4:0] REG_DDRC_T_RAS_MIN
Table 51 • DDRC_DRAM_RD_WR_TRNARND_TIME_CR
Bit
Number Name
[31:10] Reserved
[9:5] REG_DDRC_RD2WR
0×0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0×0 Present for DDR3 only (replaces REG_DDRC_T_MRD functionality
when used with DDR3 devices). The mode register set command
updates delay in number of clock cycles.
This is required to be programmed even when a design that supports
DDR3 is running in DDR2 mode (minimum is the larger of 12 clock
cycles or 15 ns).
0×0 t : Cycles between load mode commands.
MRD
Not used in DDR3 mode.
Reset
Value Description
0×0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should
be preserved across a read-modify-write operation.
t
RAS(max)
bank. Maximum time that a page can be kept open (specification:
70 µs). Minimum value of this register is 1.
Zero is invalid. Unit: Multiples of 1,024 clocks.
0×0 t
RAS(min)
same bank (specification: 45 ns).
Unit: clocks.
Reset
Value Description
0×0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should
be preserved across a read-modify-write operation.
0×0 RL + BL/2 + 2 – WL
Minimum time from READ command to WRITE command. Include
time for bus turnaround and all per-bank, per-rank, and global
constraints.
Unit: clocks.
where,
WL = Write latency
BL = Burst length. This must match the value programmed in the BL
bit of the mode register to the DRAM.
RL = Read latency = CAS latency.
Microsemi Proprietary UG0446 User Guide Revision 7.0
: Maximum time between activate and precharge to same
: Minimum time between activate and precharge to the
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