Table 13 Supported Burst Modes; Table 14 Dynamically Enforced Bank Constraints - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Supported burst modes for DDR SDRAM types and PHY widths are listed in the following table. For
M2GL050 devices, only sequential burst mode and a burst length of 8 are supported.
Table 13 • Supported Burst Modes
Bus Width Memory Type
32 LPDDR1
DDR2
DDR3
16 LPDDR1
DDR2
DDR3
8 LPDDR1
DDR3
DDR2
Note: The burst length 16 is supported for LPDDR1 if bus width is 16 except M2GL050.
3.5.5.4 Configuring Dynamic DRAM Constraints
Timing parameters for DDR memories must be configured according to the DDR memory specification.
Dynamic DRAM constraints are subdivided into three basic categories:
• Bank constraints affect the transactions that are scheduled to a given bank.
• Rank constraints affect the transactions that are scheduled to a given rank.
• Global constraints affect all transactions.
3.5.5.5 Dynamic DRAM Bank Constraints
The timing constraints which affect the transactions to a bank are listed in the following table. The control
bit field must be configured as per the DDR memory vendor specification.
Table 14 • Dynamically Enforced Bank Constraints
Timing Constraint of DDR
Memory
Row cycle time (t )
RC
Row precharge command
period (t )
RP
Minimum bank active time
(t )
RAS(min)
Maximum bank active time
(t )
RAS(max)
RAS-to-CAS delay (t )
RCD
Write command period (t
WR
Read-to-precharge delay
(t )
RTP
Control Bit
REG_DDRC_T_RC
REG_DDRC_T_RP
REG_DDRC_T_RAS_MIN
REG_DDRC_T_RAS_MAX
REG_DDRC_T_RCD
) REG_DDRC_WR2PRE
REG_DDRC_RD2PRE
Microsemi Proprietary UG0446 User Guide Revision 7.0
Sequential/Interleaving
4 8
✓ ✓
✓ ✓
– ✓
– ✓
– ✓
– ✓
– ✓
– ✓
–
Description
Minimum time between two successive activates to
a given bank.
Minimum time from a precharge command to the
next command affecting that bank.
Minimum time from an activate command to a
precharge command to the same bank.
Maximum time from an activate command to a
precharge command to the same bank.
Minimum time from an activate command to a
Read or Write command to the same bank.
Minimum time from a Write command to a
precharge command to the same bank.
Minimum time from a Read command to a
precharge command to the same bank.
Set this to the current value of additive latency plus
half of the burst length.
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