Ddr Bridge; Figure 127 Ddr Bridges In The Smartfusion2/Igloo2 Fpga Device - Microchip Technology Microsemi SmartFusion2 User Manual

DDR Bridge

5 DDR Bridge
The DDR bridge facilitates multiple AHB bus masters to access a single AXI slave and optimizes read
and write operations from multiple AHB masters to a single external DDR memory. The SmartFusion2
and IGLOO2 devices have three instances of the DDR bridge, one each for the MSS/HPMS, FDDR, and
MDDR subsystems, as shown in the following image. The DDR bridge implemented in the MSS/HPMS
(shown in red) provides an interface between AHB masters within the MSS/HPMS for accessing DDR
memory. The DDR bridge implemented in the MDDR subsystem (shown in green) provides an interface
between the user implemented AHB masters in the FPGA fabric for accessing DDR memory. Similarly,
the DDR bridge in the FDDR (shown in blue) subsystem facilitates fabric masters to access DDR
memory.
Figure 127 • DDR Bridges in the SmartFusion2/IGLOO2 FPGA Device
ARM
Cortex-M3
Processor
M
128-bit AHB
Cache
Controller
32-bit AHB
M
AHB Bus
32-bit AHB
Matrix
M
32-bit AHB
HPDMA
M
MSS/HPMS
Fabric
SmartFusion2/IGLOO2
Note: Grey blocks and arrows indicate the steps happen only in MSS. Rest are same in SmartFusion2 and IGLOO2.
The DDR bridge supports a single 64-bit AXI and up to four 32-bit AHB interfaces. For SmartFusion2 the
four MSS AHB masters are fixed, as shown in the following table. For Igloo2, the two HPMS AHB
S
S
MSS/HPMS
DDR Bridge
M
S
S
32-bit AHB
32-bit AHB
M M
AHB AHB
Master 0 Master 1
AHB AHB
Master 0 Master 1
M
M
32-bit AHB
32-bit AHB
Microsemi Proprietary UG0446 User Guide Revision 7.0
MDDR Subsystem
AXI
Transaction
64-bit AXI
Controller
S
64-bit AXI
S
M
DDR_FIC
S
DDR
Bridge
S
DDR
S
Bridge
S
DDR_FIC
M
AXI
64-bit AXI
Transaction
S
Controller
FDDR Subsystem
D
D
R
DDR
Memory
I
O
D
D
R
DDR
Memory
I
O
207