Fddr Subsystem Features Configuration; Memory Type; Bus Width Configurations - Microchip Technology Microsemi SmartFusion2 User Manual

Fabric DDR Subsystem
REG_DDRC_POWERDOWN_TO_X32 register
idle (except for issuing refreshes).
The controller automatically performs the precharge power-down exit on any of the following conditions:
• A refresh cycle is required to any rank in the system.
• The controller receives a new request from the core logic.
• REG_DDRC_POWERDOWN_EN is set to 0.
• Self refresh (DDR2, DDR3, LPDDR1)
The DDR controller keeps the DDR memory devices in Self-refresh mode whenever the
REG_DDRC_SELFREF_EN register bit
the controller.
The DDR controller can be programmed to issue single refreshes at a time
(REG_DDRC_REFRESH_BURST = 0, see
forced refresh cycle. It can be programmed to burst the maximum number of refreshes allowed for DDR
(REFRESH_BURST = 7, for performing 8 refreshes at a time) to minimize the bandwidth lost when
refreshing the pages.
The controller takes the DDR memory out of Self-refresh mode whenever the
REG_DDRC_SELFREF_EN input is deasserted or new commands are received by the controller.
When the DDR self-refresh is enabled, the DDR I/O bank may go into recalibration and a glitch may
occur in the MDDR bank I/Os, which are being used for general purpose rather than for the DDR
memory. The DDR I/Os ODT is periodically calibrated and will be effected only when the I/Os are in tri-
state (DDR I/Os are tri-stated only in self-refresh mode.
• Deep power-down (LPDDR1)
This is supported only for LPDDR1. The DDR controller puts the DDR SDRAM devices in Deep
Power-down mode whenever the REG_DDRC_DEEPPOWERDOWN_EN bit
and no reads or writes are pending in the DDR controller.
The DDR controller automatically exits Deep Power-down mode and reruns the initialization sequence
when the REG_DDRC_DEEPPOWERDOWN_EN bit is reset to 0. The contents of DDR memory may be
lost upon entry into Deep Power-down mode.
4.6.3.4.6 DRAM Initialization
After Reset, the DDR controller initializes DDR memories through an initialization sequence, depending
on the type of DDR memory used. For more information on the initialization process, refer to the JEDEC
specification.
4.6.4

FDDR Subsystem Features Configuration

The FDDR subsystem registers must be initialized before accessing DDR memory through the FDDR
subsystem. When using the System Builder flow through Libero SoC all of the necessary registers are
initialized automatically by the resulting module. This section provides the registers features of the
FDDR. All registers are listed with their bit definitions in the
page 175 section.
4.6.5

Memory Type

DDRC_MODE_CR
LPDDR1) to access memory from the FDDR subsystem.
4.6.6

Bus Width Configurations

The FDDR supports various bus widths, as listed in the following table. The FDDR can be programmed
to work in full, half, or quarter Bus width mode by configuring the DDRC_MODE_CR
and PHY_DATA_SLICE_IN_USE_CR registers
(Table 30,
Table 31,
(Table 33, page 68) must be configured to select the memory type (DDR2, DDR3, or
Microsemi ProprietaryUG0446 User Guide Revision 7.0
(Table 59, page 82) has passed, while the controller is
page 67) is set and no reads or writes are pending in
page 67) to minimize the worst-case impact of a
"FDDR Configuration Registers" section on
(Table 102, page 103) when the controller is in soft reset.
(Table 32, page 68) is set
(Table 33, page 68)
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