Microchip Technology Microsemi SmartFusion2 User Manual page 81

MDDR Subsystem
Table 35 • DDRC_ADDR_MAP_COL_1_CR
Bit
Number Name
[31:16] Reserved
[15:12] REG_DDRC_ADDRMAP_COL_B2
[11:8] REG_DDRC_ADDRMAP_COL_B3
[7:4] REG_DDRC_ADDRMAP_COL_B4 0×0
[3:0] REG_DDRC_ADDRMAP_COL_B7 0×0
Table 36 • DDRC_ADDR_MAP_COL_2_CR
Bit
Number Name
[31:16] Reserved
Reset
Value Description
0×0 Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
0×0 Full bus width mode: Selects column address bit 3.
Half bus width mode: Selects column address bit 4.
Quarter bus width mode: Selects column address bit 5.
Valid range: 0 to 7
Internal base: 2
The selected address bit is determined by adding the
internal base to the value of this field.
0×0 Full bus width mode: Selects column address bit 4.
Half bus width mode: Selects column address bit 5.
Quarter bus width mode: Selects column address bit 6.
Valid range: 0 to 7
Internal base: 3
The selected address bit is determined by adding the
internal base to the value of this field.
Full bus width mode: Selects column address bit 5.
Half bus width mode: Selects column address bit 6.
Quarter bus width mode: Selects column address bit 7.
Valid Range: 0 to 7
Internal base: 4
The selected address bit for each of the column address bits
is determined by adding the internal base to the value of this
field.
Full bus width mode: Selects column address bit 8.
Half bus width mode: Selects column address bit 9.
Quarter bus width mode: Selects column address bit 11.
Valid range: 0 to 7, and 15
Internal base: 7
The selected address bit is determined by adding the
internal base to the value of this field. If set to 15, column
address bit 9 is set to 0.
Reset
Value Description
0×0 Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
Microsemi Proprietary UG0446 User Guide Revision 7.0
Note: Per JEDEC DDR2 specification, column
address bit 10 is reserved for indicating auto-
precharge, and hence no source address bit
can be mapped to column address bit 10.
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