Table 77 Ddrc_Axi_Fabric_Pri_Id_Cr - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
Table 76 • DDRC_DYN_SOFT_RESET_ALIAS_CR (continued)
Bit
Number Name
1 RESET_APB_REG
0 REG_DDRC_SOFT_RSTB
Table 77 • DDRC_AXI_FABRIC_PRI_ID_CR
Bit
Number Name
[31:6] Reserved
[5:4] PRIORITY_ENABLE_BIT
[3:0] PRIORITY_ID
Table 78 • DDRC_SR
Bit
Number Name
[31:6] Reserved
Reset
Value
0×0
Microsemi Proprietary UG0446 User Guide Revision 7.0
Reset
Value Description
0×0 Full soft reset
If this bit is set when the soft reset bit
is written as '1', all APB registers reset
to the power-up state.
0×0 This is a soft reset.
0: Puts the controller into reset.
1: Takes the controller out of reset.
The controller should be taken out of
reset only when all other registers
have been programmed.
Asserting this bit does NOT reset all
the APB configuration registers. Once
the soft reset bit is asserted, the APB
register should be modified as
required.
Reset
Value Description
0×0 Software should not rely on the value
of a reserved bit. To provide
compatibility with future products, the
value of a reserved bit should be
preserved across a read-modify-write
operation.
0×0 This is to set the priority of the fabric
master ID.
01/10/11: Indicates that the ID is
higher priority. 00: None of the master
IDs from the fabric has a higher
priority.
0×0 If the Priority Enable bit is 1, this ID will
have a higher priority over other IDs.
Description
Software should not rely on the value of a
reserved bit. To provide compatibility with future
products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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