Use Model 1: Accessing Mddr From Fpga Fabric Through The Axi Interface; Figure 63 Mddr With Axi Interface - Microchip Technology Microsemi SmartFusion2 User Manual

MDDR Subsystem
3.12.3 Use Model 1: Accessing MDDR from FPGA Fabric Through the
AXI Interface
The MDDR subsystem can be used to access DDR memory as shown in the following illustration. This
use model follows the steps "Design flow using SmartDesign" for using MDDR. The AXI master in the
FPGA fabric accesses the DDR memory through the MDDR subsystem. The MDDR registers are
configured from FPGA fabric through the APB interface. The APB master in the FPGA fabric asserts a
ready signal to indicate that the DDR memory is successfully initialized.
The read, write, and read-modify-write transactions are initiated by the AXI master to read or write the
data into the DDR memory after receiving the ready signal from APB master.
Figure 63 • MDDR with AXI Interface
DDR
DDR
SDRAM
I/O
Use the following steps to access the MDDR from the AXI master in the FPGA fabric:
1. Instantiate the SmartFusion2 MSS component onto the SmartDesign canvas.
2. Configure the SmartFusion2 MSS peripheral components as required using the MSS configurator.
3. Configure the MDDR and select the AXI interface, as shown in the following image. In this example,
the design is created to access DDR3 memory with a 32-bit data width.
MDDR
AXI
DDR
Transaction
PHY
Controller
Controller
MSS
AXI
Slave 1
FPGA Fabric
Microsemi Proprietary UG0446 User Guide Revision 7.0
MSS DDR
Bridge
DDR_FIC
Master
Slave n
MSS
AHB
Masters
126