Table 133 Secded Dq Lines At Ddr - Microchip Technology Microsemi SmartFusion2 User Manual

Fabric DDR Subsystem
4.6.3.4.4 SECDED
The DDR controller supports built-in SECDED capability for correcting single-bit errors and detecting
dual-bit errors. The SECDED feature can be enabled. When SECDED is enabled, the DDR controller
adds 8 bits of SECDED data to every 64 bits of data.
When SECDED is enabled, a write operation computes and stores a SECDED code along with the data,
and a read operation reads and checks the data against the stored SECDED code.
The SECDED bits are interlaced with the data bits, as shown in the following table.
Table 133 • SECDED DQ Lines at DDR
Mode
Full bus width mode
Half bus width mode
Quarter bus width mode
When the controller detects a correctable SECDED error, it does the following:
• Generates an interrupt signal which can be monitored by reading the interrupt status register,
DDRC_ECC_INT_SR
which can be monitored from FPGA fabric.
• Sends the corrected data to the read requested MSS/HPMS and FPGA fabric master as part of the
read data.
• Sends the SECDED error information to the DDRC_LCE_SYNDROME_1_SR register,
page 96.
• Performs a read-modify-write operation to correct the data present in the DRAM.
When the controller detects an uncorrectable error, it does the following:
• Generates an interrupt signal that can be monitored by reading the interrupt status register
DDRC_ECC_INT_SR,
signal, which can be monitored from FPGA fabric.
• Sends the data with error to the read requested MSS/HPMS and FPGA fabric master as part of the
read data.
• Sends the SECDED error information to the DDRC_LUE_SYNDROME_1_SR register,
page 92.
The following SECDED Registers in
of an error in the DDR SDRAM.
• DDRC_LUE_ADDRESS_1_SR and DDRC_LUE_ADDRESS_2_SR gives the row/bank/column
information of the SECDED unrecoverable error.
• DDRC_LCE_ADDRESS_1_SR and DDRC_LCE_ADDRESS_2_SR gives the row/bank/column
information of the SECDED error correction.
• DDRC_LCB_NUMBER_SR indicates the location of the bit that caused the single-bit error in the
SECDED case (encoded value).
• DDRC_ECC_INT_SR indicates whether the SECDED interrupt is because of a single-bit error or
double-bit error. The interrupt can be cleared by writing zeros to DDRC_ECC_INT_CLR_REG,
Table 101,
4.6.3.4.5 Power Saving Modes
The DDR controller can operate DDR memories in three power saving modes:
• Precharge power-down (DDR2, DDR3, LPDDR1)
If power-down is enabled in the System Builder FDDR configuration or
REG_DDRC_POWERDOWN_EN = 1
memory in Precharge power-down mode when the period specified by the power down entry time or
SECDED Data Pins
M2S050/M2GL050 (FG896)
FDDR_DQ_ECC[3:0]
FDDR_DQ_ECC[1:0]
–
(Table 100, page 102). The FDDR also generates ECCINT interrupt signal,
Table 100, page 102. The FDDR also generates an ECC_INT interrupt
Table 28,
page 102.
(Table 32,
Microsemi ProprietaryUG0446 User Guide Revision 7.0
M2S150/M2GL150 (FC1152)
FDDR_DQ_ECC[3:0]
FDDR_DQ_ECC[1:0]
FDDR_DQ_ECC[0]
page 63 can be monitored for identifying the exact location
page 68), the DDR controller automatically keeps DDR
Table 88,
Table 81,
151