Revision History; Revision 7.0; Revision 6.0; Revision 5.0 - Microchip Technology Microsemi SmartFusion2 User Manual

Revision History

1 Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.
1.1

Revision 7.0

The following is a summary of the changes in this revision.
• Read and Write leveling is not supported. Removed information about all the Read and Write
leveling registers.
• Most of the PHY registers have been reserved.
1.2

Revision 6.0

The following is a summary of the changes in this revision.
• Updated
Calibration,
1.3

Revision 5.0

The following is a summary of the changes in this revision.
• Updated
62858).
• Updated
• Updated
• Updated
• Updated
• Added DDR Memory Initialization Time,
• Updated
1.4

Revision 4.0

The following is a summary of the changes in this revision.
• Merged SmartFuion2 and IGLOO2 User Guides.
• Updated
• Updated
49186, 52819, 54053, 51933, 55041, 52727, 48832).
• Updated
68400, 64575, 65164, and 69655).
• Updated
• Updated
• Updated
1.5

Revision 3.0

The following is a summary of the changes in this revision.
• Updated the Part Numbers (M2S075 to M2S090, M2S080 to M2S100, and M2S120 to M2S150) as
required (SAR 47554).
• Updated
62955).
• Updated
• Updated
1.6

Revision 2.0

The following is a summary of the changes in this revision.
I/O Utilization, page 7, I/O Utilization,
page 145 (SAR 81073).
MDDR Subsystem, page 5 and
Table 2, page 7, Table 4, page 7,
Initialization, page 16 and Power Saving Modes,
Table 86, page 95, Table 87,
Architecture Overview, page 136 (SAR 79005).
Appendix B: Register Lock Bits Configuration,
Additional Documentation,
MDDR Subsystem, page 5 and
MDDR Subsystem, page 5 (SARs 62441, 66225, 60914, 69568, 66860, 69611, 69261,
Fabric DDR Subsystem, page 134 (SARs 62441, 60914, 66860, 69144, and 54429).
DDR Bridge, page 207.
Soft Memory Controller Fabric Interface Controller,
MDDR Subsystem, page 5 (SARs 47919, 48832, 49947, 50561, 50732, 62858, and
Fabric DDR Subsystem, page 134 (SARs 62858 and 62955).
Soft Memory Controller Fabric Interface Controller,
Microsemi Proprietary UG0446 User Guide Revision 7.0
page 136, DDRIO Calibration,
Fabric DDR Subsystem,
Table 11, page 24 (SAR 78912).
page 24 (SAR 52819).
page 95, Table 93, page 99,
page 18 (SAR 72725).
page 204 (SAR 79864).
page 3 (SAR 68482).
Fabric DDR Subsystem,
page 219.
page 219 (SAR 48330).
page 16, and DDRIO
page 134 (SARs 62955 and
Table 94, page 99 (SAR 75057).
page 134 (SARs 55467, 54300,
1