Reference Clock Selection And Distribution - Xilinx Virtex UltraScale+ FPGAs User Manual

Figure 5:
MGTAVCC
GTREFCLKP
GTREFCLKN
Ports and Attributes
The following table defines the ports in the OBUFDS_GTM software primitive.
Table 5: Reference Clock Output Ports (OBUFDS_GTM)
Port Dir
CEB In
I In (pad)
O In (pad)
OB Out
The following table defines the attributes in the OBUFDS_GTM software primitive that configure
the reference clock output.
Table 6: Reference Clock Output Attributes (OBUFDS_GTM)
Attribute
REFCLK_EN_TX_PATH
REFCLK_ICNTL_TX

Reference Clock Selection and Distribution

The GTM transceivers in Virtex UltraScale+ FPGAs provide different reference clock input
options. Clock selection and availability is similar to the GTY transceivers in UltraScale+ devices,
but the reference clock selection architecture supports only one LCPLL shared per Dual (two
GTM transceiver channels).
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Reference Clock Output Use Model for OBUFDS_GTM
OBUFDS_GTM
O
OB
Clock Domain
N/A This is the active-Low asynchronous clock enable signal for the clock buffer.
Setting this signal High powers down the clock buffer.
N/A Recovered clock input. Connect to the output port RXRECCLK0/1 of the
GTM_DUAL primitive.
N/A Reference clock output port that gets mapped to GTREFCLKP.
N/A Reference clock output port that gets mapped to GTREFCLKN.
Type
1-bit
5-bit
From RXRECCLK0/1
of GTM_DUAL
Description
Description
Reserved. This attribute must always be set to 1'b1.
Reserved. Use the recommended value from the Wizard.
Send Feedback
Chapter 2: Shared Features
I
CEB
X20877-061418
www.xilinx.com
14