Xilinx Virtex UltraScale+ FPGAs User Manual page 135

Gtm transceivers
Table of Contents

Advertisement

Table 75: DRP Map of GTM_DUAL Primitive (cont'd)
DRP
DRP
Addres
Bits
s
0x039
[15:0]
0x03a
[15:0]
0x03b
[15:0]
0x03c
[15:0]
0x03d
[15:0]
0x03e
[15:0]
0x03f
[15:0]
0x040
[15:0]
0x041
[15:0]
0x042
[15:0]
0x043
[15:0]
0x044
[15:0]
0x045
[15:0]
0x046
[15:0]
0x047
[15:0]
0x048
[15:0]
0x049
[15:0]
0x04a
[15:0]
0x04b
[15:0]
0x04c
[15:0]
0x04d
[15:0]
0x04e
[15:0]
0x04f
[15:0]
0x050
[15:0]
0x051
[15:0]
0x052
[15:0]
0x053
[15:0]
0x054
[15:0]
0x055
[15:0]
0x056
[15:0]
0x057
[15:0]
0x058
[15:0]
0x059
[15:0]
0x05a
[15:0]
0x05b
[15:0]
0x05c
[15:0]
0x064
[15:0]
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Appendix A: DRP Address Map of the GTM Transceiver in UltraScale+ FGPAs
R/W
Attribute Name
R/W
CH0_RX_APT_CFG11B
R/W
CH0_RX_APT_CFG12A
R/W
CH0_RX_APT_CFG12B
R/W
CH0_RX_APT_CFG13A
R/W
CH0_RX_APT_CFG13B
R/W
CH0_RX_APT_CFG14A
R/W
CH0_RX_APT_CFG14B
R/W
CH0_RX_APT_CFG15A
R/W
CH0_RX_APT_CFG15B
R/W
CH0_RX_APT_CFG16A
R/W
CH0_RX_APT_CFG16B
R/W
CH0_RX_APT_CFG17A
R/W
CH0_RX_APT_CFG17B
R/W
CH0_RX_APT_CFG18A
R/W
CH0_RX_APT_CFG18B
R/W
CH0_RX_APT_CFG19A
R/W
CH0_RX_APT_CFG19B
R/W
CH0_RX_APT_CFG20A
R/W
CH0_RX_APT_CFG20B
R/W
CH0_RX_APT_CFG21A
R/W
CH0_RX_APT_CFG21B
R/W
CH0_RX_APT_CFG28A
R/W
CH0_RX_APT_CFG28B
R/W
CH0_RX_APT_CFG22A
R/W
CH0_RX_APT_CFG22B
R/W
CH0_RX_APT_CFG23A
R/W
CH0_RX_APT_CFG23B
R/W
CH0_RX_APT_CFG24A
R/W
CH0_RX_APT_CFG24B
R/W
CH0_RX_APT_CFG25A
R/W
CH0_RX_APT_CFG25B
R/W
CH0_RX_APT_CFG26A
R/W
CH0_RX_APT_CFG26B
R/W
CH0_RX_APT_CFG27A
R/W
CH0_RX_APT_CFG27B
R/W
CH0_RX_DSP_CFG
R/W
CH0_RX_CAL_CFG2A
Attribute
Attribute Bits
Encoding
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
[15:0]
0–65535
www.xilinx.com
Send Feedback
DRP
Encoding
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
135

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents