Xilinx Virtex UltraScale+ FPGAs User Manual page 26

Table 12: GTM Transceiver Reset Modes Ports
Port
CH[0/1]_RXRESETMODE[1:0]
CH[0/1]_TXRESETMODE[1:0]
LCPLL Reset
The LCPLL must be reset before it can be used. Each GTM transceiver dual has dedicated reset
ports for its LCPLL. As shown in the figure, PLLRESET is an input that resets LCPLL. PLLLOCK is
an output that indicates the reset process is done. The guideline for this asynchronous PLLRESET
pulse width is one period of the reference clock. After a PLLRESET pulse, the internal reset
controller generates an internal LCPLL reset followed by an internal SDM reset. The time
required for LCPLL to lock is affected by a few factors, such as bandwidth setting and clock
frequency.
Table 13: LCPLL Reset Ports
Port
PLLRESET
PLLRESETMASK[1:0]
PLLRESETBYPASSMODE
PLLLOCK
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Direction Clock Domain
In
In
LCPLL Reset Timing Diagram
Figure 12:
Clock
Dir
Domain
In Async Active-High signal that resets the LCPLL.
In Async Reserved. Tied to 2'b11.
In Async Reserved. Tied Low.
Out Async Active-High LCPLL frequency lock signal indicates that the
LCPLL frequency is within a predetermined tolerance. The
GTM transceiver and its clock outputs are not reliable until
this condition is met.
Chapter 2: Shared Features
Description
Async Reset mode port for RX.
2'b00: Sequential mode
(recommended).
2'b01: Reserved.
2'b10: Reserved.
2'b11: Single mode.
Async Reset mode port for TX.
2'b00: Sequential mode
(recommended).
2'b01: Reserved.
2'b10: Reserved.
2'b11: Single mode.
Description
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