Xilinx Virtex UltraScale+ FPGAs User Manual page 139

Table 75: DRP Map of GTM_DUAL Primitive (cont'd)
DRP
DRP
Addres
Bits
s
0x201 [15:0]
0x202 [15:0]
0x203 [15:0]
0x204 [15:0]
0x205 [15:0]
0x206 [15:0]
0x207 [15:0]
0x208 [15:0]
0x209 [15:0]
0x20a [15:0]
0x20b [15:0]
0x20c [15:0]
0x20d [15:0]
0x20e [15:0]
0x20f [15:0]
0x210 [15:0]
0x211 [15:0]
0x212 [15:0]
0x213 [15:0]
0x214 [15:0]
0x215 [15:0]
0x216 [15:0]
0x217 [15:0]
0x218 [15:0]
0x219 [15:0]
0x21a [15:0]
0x21b [15:0]
0x21c [15:0]
0x21d [15:0]
0x21e [15:0]
0x21f [15:0]
0x220 [15:0]
0x221 [15:0]
0x222 [15:0]
0x223 [15:0]
0x224 [15:0]
0x225 [15:0]
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Appendix A: DRP Address Map of the GTM Transceiver in UltraScale+ FGPAs
R/W Attribute Name
R/W CH1_TX_DRV_CFG0
R/W CH1_TX_DRV_CFG1
R/W CH1_TX_DRV_CFG2
R/W CH1_TX_ANA_CFG1
R/W CH1_TX_ANA_CFG2
R/W CH1_TX_ANA_CFG3
R/W CH1_TX_DRV_CFG3
R/W CH1_TX_DRV_CFG4
R/W CH1_TX_DRV_CFG5
R/W CH1_TX_LPBK_CFG0
R/W CH1_TX_LPBK_CFG1
R/W CH1_TX_ANA_CFG4
R/W CH1_TX_CAL_CFG0
R/W CH1_TX_CAL_CFG1
R/W CH1_TX_ANA_CFG0
R/W CH1_RX_ANA_CFG0
R/W CH1_RX_ANA_CFG1
R/W CH1_RX_PAD_CFG0
R/W CH1_RX_PAD_CFG1
R/W CH1_RX_CDR_CFG4A
R/W CH1_RX_CDR_CFG4B
R/W CH1_RX_CDR_CFG3A
R/W CH1_RX_CDR_CFG3B
R/W CH1_RX_CDR_CFG2A
R/W CH1_RX_CDR_CFG2B
R/W CH1_RX_CDR_CFG1A
R/W CH1_RX_CDR_CFG1B
R/W CH1_RX_CDR_CFG0A
R/W CH1_RX_CDR_CFG0B
R/W CH1_RX_CLKGN_CFG1
R/W CH1_RX_ANA_CFG2
R/W CH1_RX_APT_CTRL_CFG2
R/W CH1_RX_APT_CTRL_CFG3
R/W CH1_RX_APT_CFG0A
R/W CH1_RX_APT_CFG0B
R/W CH1_RX_APT_CFG1A
R/W CH1_RX_APT_CFG1B
Attribute
Attribute Bits
Encoding
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
[15:0] 0–65535
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DRP
Encoding
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
0–65535
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