Xilinx Virtex UltraScale+ FPGAs User Manual page 83

Table 46: TX Configurable Driver Ports (cont'd)
Port
CH[0/1]_TXMUXDCDORWREN
The following table defines the TX configurable driver attributes.
Table 47: TX Configurable Driver Attributes
Attribute
CH[0/1]_TX_ANA_CFG1
Bit Name
TXMODSEL
CH[0/1]_TX_DRV_CFG0
Bit Name
TXEMPMAIN_INDEP
Use Modes
The GTM TX has the ability to transmit serial data using two different modulation schemes: NRZ
and PAM4. NRZ signals contains one bit of information per symbol, while PAM4 signals contain
two bits of information per symbol. Using PAM4 modulation doubles the transmitted data
bandwidth while maintaining the same unit interval (UI). To program the GTM TX to a desired
signal modulation mode, the user must configure the attribute TXMODSEL for CH0 or CH1.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Clock
Dir
Domain
Input Async Reserved. Use the recommended value from the Wizard.
Type
16-bit
Address
[7]
16-bit
Address
[0]
Chapter 3: Transmitter
Description
Description
Reserved.
Description
Driver output modulation control:
1'b0: PAM4 modulation.
1'b1: NRZ modulation.
Reserved.
Description
Allows independent control of the main cursor:
1'b0: The CH[0/1]_TXEMPMAIN coefficient is
automatically determined.
1'b1: CH[0/1]_TXEMPMAIN coefficient can be
independently set by the CH[0/1]_TXEMPMAIN
pins within the range specified in the pin
description.
Send Feedback
www.xilinx.com
83