Xilinx Virtex UltraScale+ FPGAs User Manual page 7

Table 1: GTM Transceiver Features (cont'd)
Group
LC tank oscillator PLL (LCPLL) for best jitter performance
Flexible clocking with one PLL per Dual (two channels)
Programmable TX output
TX FIR filter with de-emphasis controls
PMA
Continuous time linear equalizer (CTLE)
Decision feedback equalization (DFE)
Feed forward equalization (FFE)
Notes:
1. A dual is a cluster or set of two GTM transceiver channels. One GTM_DUAL primitive, one differential reference clock
pin pair, and analog supply pins. There is no channel primitive.
The GTM transceiver supports NRZ and PAM4 modulation as well as the following protocols:
• 100GE CAUI2
• 100GE CAUI4
• 200GE CCAUI4
• 400GE (CDAUI8)
• 50GE LAUI
• 50GE LAUI2
• Ethernet AN/LT (auto negotiation/link training)
• OTU4
• Interlaken at 53.125 Gb/s, 25.78125 Gb/s, and 12.5 Gb/s
• CPRI at 48 Gb/s, 24 Gb/s, 12 Gb/s, and 10.1 Gb/s
The first-time user is recommended to read
high-speed serial transceiver technology and its applications. The Xilinx Vivado
includes an UltraScale+ FPGAs GTM Transceivers Wizard to automatically configure GTM
transceivers to support configurations for different protocols and perform custom configurations.
The GTM transceiver offers a data rate range and features that allow physical layer support for
various protocols. The following figure illustrates the clustering of one GTM_DUAL primitive.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Chapter 1: Transceiver and Tool Overview
Feature
High-Speed Serial I/O Made
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