Xilinx Virtex UltraScale+ FPGAs User Manual page 13

Ports and Attributes
The following table defines the reference clock input ports in the IBUFDS_GTM software
primitive.
Table 3: Reference Clock Input Ports (IBUFDS_GTM)
Port Dir
CEB In
I In (pad)
IB In (pad)
O Out
ODIV2 Out
The following table defines the attributes in the IBUFDS_GTM software primitive that configure
the reference clock input.
Table 4: Reference Clock Input Attributes (IBUFDS_GTM)
Attribute
REFCLK_EN_TX_PATH
REFCLK_HROW_CK_SEL
REFCLK_ICNTL_RX
Output Mode
The reference clock output mode can be accessed via the OBUFDS_GTM software primitive. The
reference clock output mode structure for the OBUFDS_GTM primitive is shown in the following
figure. The ports and attributes controlling the reference clock output are tied to the
OBUFDS_GTM software primitive.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Clock Domain
N/A This is the active-Low asynchronous clock enable signal for the clock buffer.
Setting this signal High powers down the clock buffer.
N/A These are the reference clock input ports that get mapped to GTREFCLKP.
N/A These are the reference clock input ports that get mapped to GTREFCLKN.
N/A This output drives the GTREFCLK signal in the GTM_DUAL software primitive.
Refer to Reference Clock Selection and Distribution
N/A This output can be configured to output either the O signal or a divide-by-2
version of the O signal. It can drive the BUFG_GT via the HROW routing. Refer
to Reference Clock Selection and Distribution
Type
1-bit
2-bit
2-bit
Description
Description
Reserved. This attribute must always be set to 1'b0.
Configures the ODIV2 output port:
2'b00: ODIV2 = O.
2'b01: ODIV2 = Divide-by-2 version of O.
2'b10: ODIV2 = 1'b0.
2'b11: ODIV2 = Reserved.
Reserved. Use the recommended value from the Wizard.
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