Xilinx Virtex UltraScale+ FPGAs User Manual page 78

4-Tap
PISO
FIR
Ports and Attributes
The following table defines the TX configurable driver ports.
Table 46: TX Configurable Driver Ports
Port
CH[0/1]_TXDRVAMP[4:0]
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
TX Configurable Driver Block Diagram
Figure 35:
CH0/1_TXEMPPRE2[3:0]
Pre-Emphasis 2
Pad Driver
CH0/1_TXEMPPRE[4:0]
Pre-Emphasis
Pad Driver
CH0/1_TXDRVAMP[4:0]
Main
Pad Driver
CH0/1_TXEMPPOST[4:0]
Post-Emphasis
Pad Driver
Clock
Dir
Domain
Input Async
Description
Driver swing control. The default is user specified. All listed
values are in mV .
PPD
[4:0]
5'b00000
5'b00001
5'b00010
5'b00011
5'b00100
5'b00101
5'b00110
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Chapter 3: Transmitter
50Ω
CH0/1_GTMTXP
50Ω
CH0/1_GTMTXN
X20916-060618
mV
PPD
250
275
300
325
350
375
400
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