Xilinx Virtex UltraScale+ FPGAs User Manual page 79

Table 46: TX Configurable Driver Ports (cont'd)
Port
CH[0/1]_TXINHIBIT
CH[0/1]_TXEMPMAIN[5:0]
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Clock
Dir
Domain
Notes:
1. The peak-to-peak differential voltage is defined when
CH[0/1]_TXEMPPOST = 5'b00000, CH[0/1]_TXEMPPRE =
5'b00000, and CH[0/1]_TXEMPPRE2 = 4'b0000.
2. For UltraScale+ FPGAs, the output swing described above
is obtained using settings from the Wizard design, and the
recommended values from the Wizard should not be
changed.
Input TXUSRCLK2 When High, this signal blocks transmission of CH[0/1]_TXDATA
and forces CH[0/1]_GTMTXP to 0 and CH[0/1]_GTMTXN to 1.
Input Allows the main cursor coefficients to be directly set if
CH[0/1]_TX_DRV_CFG0[0] attribute is set to 1'b1.
CH[0/1]_TXDRVAMP should be used together with
CH[0/1]_TXEMPMAIN to achieve the desired TX output swing.
Chapter 3: Transmitter
Description
5'b00111
5'b01000
5'b01001
5'b01010
5'b01011
5'b01100
5'b01101
5'b01110
5'b01111
5'b10000
5'b10001
5'b10010
5'b10011
5'b10100
5'b10101
5'b10110
5'b10111
5'b11000
5'b11001
5'b11010
5'b11011
5'b11100
5'b11101
5'b11110
5'b11111
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