Xilinx Virtex UltraScale+ FPGAs User Manual page 86

Table 48: RX AFE ports (cont'd)
Ports
BGRCALOVRD[4:0]
BGRCALOVRDENB
RCALENB
The following table defines the RX AFE attributes.
Table 49: RX AFE Attributes
Attribute
CH[0/1]_RX_PAD_CFG0
Bit Name
PAD_RTERM_VCOM_MODE
PAD_RTERM_VCOM_LVL
GTM Use Modes - RX Termination
This section describes the GTM use modes with RX termination.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Dir Clock Domain
In Async
In Async
In Async
Type
16-bit Reserved.
Address Description
[12:11] Controls the mode for the RX termination voltage:
2'b00: AVTT
2'b01: Reserved
2'b10: Floating
2'b11: Programmable
[10:7] Controls the common mode in programmable mode:
4'b0000: 100 mV
4'b0001: 200 mV
4'b0010: 250 mV
4'b0011: 300 mV
4'b0100: 350 mV
4'b0101: 400 mV
4'b0110: 500 mV
4'b0111: 550 mV
4'b1000: 600 mV
4'b1001: 700 mV
4'b1010: 800 mV
4'b1011: 850 mV
4'b1100: 900 mV
4'b1101: 950 mV
4'b1110: 1000 mV
4'b1111: 1100 mV
Chapter 4: Receiver
Description
Reserved. This port must be set to
5'b11111. Do not modify this value.
Reserved. This port must be set to 1'b1.
Do not modify this value.
Reserved. This port must be set to 1'b1.
Do not modify this value.
Description
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