Xilinx Virtex UltraScale+ FPGAs User Manual page 58

Table 30: TX Interface Ports (cont'd)
Port
TXUSRCLK2
The following table defines the TX interface attributes.
Table 31: TX Interface Attributes
Attribute
CH[0/1]_TX_PCS_CFG0
Bit Name
TX_DATA_WIDTH
TX_INT_DATA_WIDTH
GEN_TXUSRCLK
CH[0/1]_A_CH_CFG0
Bit Name
TX_FABINT_USRCLK_FLOP
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Dir Clock Domain
In Clock
Type
3-bit Reserved.
Address Description
[2:0] Sets the bit width of the TXDATA port. When FEC is enabled,
TX_DATA_WIDTH must be set to 160:
[4:3] Controls the width of the internal TX PCS datapath. 80-bit
internal datapath must be used with 80- or 160-bit fabric
width; 128-bit internal datapath must be used with 128- or
256-bit fabric width; 64-bit internal datapath must be used
with 64- or 128-bit fabric width:
[14] Automatically generate TXUSRCLK from TXUSRCLK2. This is
only applicable when the fabric datapath width is the same as
the internal datapath width.
1-bit Reserved.
Address Description
[0] Determines if port signals are registered again in the
TXUSRCLK domain after being registered in the TXUSRCLK2
domain. This attribute only applies if the TX internal datapath
width is the same as the TX interface width, otherwise this
attribute is ignored. Use the recommended value from the
Wizard:
Description
This port is used to synchronize the interconnect
logic with the TX interface. This clock must be
positive-edge aligned to TXUSRCLK.
Description
0x0: 64-bit fabric mode.
0x1: 80-bit fabric mode.
0x2: 128 bit fabric mode.
0x3: 160-bit fabric mode.
0x4: 256-bit fabric mode.
0x0: 64-bit internal datapath mode.
0x1: 80-bit internal datapath mode.
0x2: 128-bit internal datapath mode.
0x0: Disable automatic TXUSRCLK generation from
TXUSRCLK2.
0x1: Enable automatic TXUSRCLK generation from
TXUSRCLK2.
0x0: Bypass TXUSRCLK flip-flops.
0x1: Enable TXUSRCLK flip-flops.
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