Xilinx Virtex UltraScale+ FPGAs User Manual page 33

Table 16: Recommended Transmitter Resets for Common Situations (cont'd)
Situation
After assertion/
deassertion of TXPD
TX rate change
TX parallel clock source
reset
Notes:
1. TXPCSRESETMASK[0] can be set to 0 if the FEC is bypassed.
After Power-up and Configuration
The PLL being used and the entire GTM TX require a reset after configuration. See
Transceiver TX Reset in Response to Completion of
After Turning on a Reference Clock to the LCPLL/
RPLL Being Used
If the reference clock(s) changes or the GTM transceiver(s) are powered up after configuration,
perform a full TX sequential reset after the PLL fully completes its reset procedure.
After Changing the Reference Clock to the PLL being
Used
Whenever the reference clock input to the PLL is changed, the PLL must be reset afterwards to
ensure that it locks to the new frequency. Perform a full TX sequential reset after the PLL fully
completes its reset procedure.
After Assertion/Deassertion of PLLPD for the PLL
being Used
When the PLL being used goes back to normal operation after power down, the PLL must be
reset. Perform a full TX sequential reset after the PLL fully completes its reset procedure.
After Assertion/Deassertion of TXPD[1:0]
After the TXPD signal is deasserted, perform a full TX sequential reset.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Components to
be Reset
TXRESETMODE
Entire TX
2'b00
TX PMA and TX PCS
2'b00
TX PCS
2'b00/2'b11
Chapter 2: Shared Features
Recommended TX Reset Setting
TXPMARESETMASK
2'b11
2'b11
2'b00
Configuration.
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1
TXPCSRESETMASK
2'b11
2'b11
2'b11
GTM
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