Xilinx Virtex UltraScale+ FPGAs User Manual page 88

The combination of CTLE, FFE, and DFE can compensate for both the pre-cursor and post-cursor
of the transmitted bit. All equalization loops are auto-adaptive to handle a wide range of channel
profiles and to compensate for any PVT variations.
P
CTLE
N
Ports and Attributes
The following table defines the RX equalizer ports.
Table 50: RX Equalizer Ports
Port
CH[0/1]_RXADAPTRESET
CH[0/1]_RXADCCALRESET
CH[0/1]_RXADCCLKGENRESET
CH[0/1]_RXDFERESET
CH[0/1]_RXDSPRESET
CH[0/1]_RXEQTRAINING
The following table defines the RX equalizer attributes.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
GTM RX Equalization
Figure 39:
ADC
AGC
Dir
In
In
In
In
In
In
CDR
FFE DFE
Adaptation
Controller
Clock Domain
Async This port is driven High and then deasserted
to start a single-mode reset on RX adaptation.
The reset is not dependent on RXRESETMODE
or RXPMARESETMASK setting.
Async Reserved. Tie to 1'b0.
Async This port is driven High and then deasserted
to start a single-mode reset on the RX ADC
CLKGEN. The reset is not dependent on
RXRESETMODE or RXPMARESETMASK setting.
Async This port is driven High and then deasserted
to start a single-mode reset on the DFE. The
reset is not dependent on RXRESETMODE or
RXPMARESETMASK setting.
Async This port is driven High and then deasserted
to start a single-mode reset on the DSP. The
reset is not dependent on RXRESETMODE or
RXPMARESETMASK setting.
Async Reserved. Tie to 1'b0.
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