Xilinx Virtex UltraScale+ FPGAs User Manual page 59

Using TXPROGDIVCLK to Drive the TX Interface
Depending on the TXUSRCLK and TXUSRCLK2 frequencies, there are different ways UltraScale
architecture clock resources can be used to drive the parallel clock for the TX interface.
through Figure 29
for the TX interface.
Depending on the input reference clock frequency and the required line rate, a BUFG_GT with a
properly configured divide setting is required. The UltraScale+ FPGAs GTM Transceivers Wizard
creates a sample design based on different design requirements for most cases.
TXPROGDIVCLK Driving GTM Transceiver TX in 64-Bit, 80-Bit, or 128-
Bit Mode
In the following figure, TXPROGDIVCLK is used to drive TXUSRCLK and TXUSRCLK2 in 64-bit,
80-bit, or 128-bit mode in a single-lane configuration. In all cases, the frequency of TXUSRCLK2
is equal to TXUSRCLK.
Single Lane—TXPROGDIVCLK Drives TXUSRCLK and TXUSRCLK2 (64-Bit, 80-
Figure 26:
UltraScale
Devices GTM
Transceiver
Notes relevant to the figure:
1. For details about placement constraints and restrictions on clocking resources (such as
BUFG_GT and BUFG_GT_SYNC), refer to the UltraScale Architecture Clocking Resources User
Guide (UG572).
2. F = F
TXUSRCLK2
3. TXUSRCLK can be tied to 1'b0 if GEN_TXUSRCLK = 1'b1.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
show different ways clock resources can be used to drive the parallel clocks
Bit, or 128-Bit Mode)
BUFG_GT
TXPROGDIVCLK
2
TXUSRCLK2
2,3
TXUSRCLK
TXDATA (TX data width = 64/80/128 bits)
.
TXUSRCLK
1
Design in UltraScale
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Chapter 3: Transmitter
Figure 26
Architecture
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