Tx Pattern Generator - Xilinx Virtex UltraScale+ FPGAs User Manual

Ports and Attributes
The following table defines the TX buffer ports.
Table 35: TX Buffer Ports
Port
CH[0/1]_TXBUFSTATUS[1:0]
The following table defines the TX buffer attributes.
Table 36: TX Buffer Attributes
Attribute
CH[0/1]_TX_PCS_CFG0
CH[0/1]_TXFIFO_UNDERFLOW
CH[0/1]_TXFIFO_OVERFLOW

TX Pattern Generator

Pseudo-random it sequences (PRBS) are commonly used to test the signal integrity of high-speed
links. These sequences appear random but have specific properties that can be used to measure
the quality of a link. The GTM transceiver pattern generator block can generate several industry-
standard PRBS patterns listed in the following table.
Table 37: Supported PRBS Patterns
Name
PRBS-7
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Dir
Out
Type
16-bit
1-bit
1-bit
Length of
Polynomial
Sequence
1 + x 6 + x 7 2 7
Clock Domain
TXUSRCLK TX buffer status:
Reserved. Use the recommended value from the Wizard.
A value of 1 indicates FIFO underflow.
For channel 0, bit[8] of DRP address 0x489
For channel 1, bit[8] of DRP address 0x689
:
Note This is a read-only attribute.
A value of 1 indicates FIFO overflow.
For channel 0, bit[9] of DRP address 0x489
For channel 1, bit[9] of DRP address 0x689
:
Note This is a read-only attribute.
– 1 bits Used to test channels with 8B/10B.
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Chapter 3: Transmitter
Description
Bit[1]: FIFO overflow status. A value of
1 indicates FIFO overflow.
Bit[0]: FIFO underflow status. A value
of 1 indicates FIFO underflow.
Description
Description
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