Xilinx Virtex UltraScale+ FPGAs User Manual page 114

RXUSRCLK and RXUSRCLK2 Generation
The RX interface includes two parallel clocks: RXUSRCLK and RXUSRCLK2. RXUSRCLK is the
internal clock for the PCS logic in the GTM transmitter. The required rate for RXUSRCLK
depends on the internal datapath width of the GTM_DUAL primitive and the RX line rate of the
GTM transmitter. The following
RXUSRCLK for all cases.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
RX Data Received
Figure 45:
equation shows how to calculate the required rate for
RXUSRCLK Rate =
Line Rate
Internal Datapath Width
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Chapter 4: Receiver
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