Xilinx Virtex UltraScale+ FPGAs User Manual page 19

The LCPLL input clock selection is described in
LCPLL outputs feed the TX and RX clock divider blocks, which control the generation of serial
and parallel clocks used by the PMA and PCS blocks. The LCPLL is shared between the TX and
RX datapaths.
The figure below illustrates a conceptual view of the LCPLL architecture. The input clock can be
divided by a factor of M before it is fed into the phase frequency detector. The feedback divider
N determines the voltage-controlled oscillator (VCO) multiplication ratio. For line rates below
28.1 Gb/s (NRZ) and 56.2 Gb/s (PAM4), a fractional-N divider is supported where the effective
ratio is a combination of the N factor plus a fractional part. The LCPLL output frequency depends
on the settings of LCPLLCLKOUT_RATE. When LCPLLCLKOUT_RATE is set to HALF, the output
frequency is half of the VCO frequency. When it is set to FULL, the output frequency is the same
as the VCO frequency. A lock indicator block compares the frequencies of the reference clock
and VCO feedback clock to determine if a frequency lock has been achieved.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Internal Dual Clocking Architecture
Figure 9:
GTM_DUAL
LCPLL
GTM Channel 0 (CH0)
TX PMA
TX PCS
RX PMA
RX PCS
GTM Channel 1 (CH1)
TX PMA
TX PCS
RX PMA
RX PCS
Reference Clock Selection and
Send Feedback
Chapter 2: Shared Features
X20900-061418
Distribution. The
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