Xilinx Virtex UltraScale+ FPGAs User Manual page 17

Figure 8:
MGTREFCLKP
MGTREFCLKN
:
Note The IBUFDS_GTM diagram in the above figure is a simplification. The output port ODIV2 is left
floating, and the input port CEB is set to logic 0.
These rules must be observed when sharing a reference clock to ensure that jitter margins for
high-speed designs are met:
• The number of Duals above the sourcing Dual must not exceed one.
• The number of Duals below the sourcing Dual must not exceed one.
• The total number of Duals sourced by an external clock pin pair (MGTREFCLKP/
MGTREFCLKN) must not exceed three Duals.
The maximum number of Duals that can be sourced by a single clock pin pair is three (six
transceivers). Designs with more than three Duals require the use of multiple external clock pins
to ensure that the rules for controlling jitter are followed. When multiple clock pins are used, an
external buffer can be used to drive them from the same oscillator.
IMPORTANT! Upon device configuration, the clock output from the IBUFDS_GTM which takes inputs
from MGTREFCLKP and MGTREFCLKN can only be used as long as the GTPOWERGOOD signal has
already asserted High.
Ports and Attributes
The following table defines the clocking ports and attributes for the GTM_DUAL primitive.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Single External Reference Clock with Multiple Duals
IBUFDS_GTM
I
O
IB
Chapter 2: Shared Features
D(n+1)
GTM_DUAL
GTREFCLK
D(n)
GTM_DUAL
GTREFCLK
D(n-1)
GTM_DUAL
GTREFCLK
X20215-061418
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