Xilinx Virtex UltraScale+ FPGAs User Manual page 96

Table 54: RX Programmable Divider Ports
Port
CH[0/1]_RXPROGDIVRESET
CH[0/1]_RXPRGDIVRESETDONE
CH[0/1]_RXPROGDIVCLK
Table 55: RX Programmable Divider Attribute
Attribute
CH[0/1]_RX_ANA_CFG1
Bit Name
RX_PROGDIV_SELFR
RX_PROGDIV_SEL_DIV66
RX_PROGDIV_SEL_DIV5
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Dir Clock Domain
In Async
Out Async
Out Clock
Type
16-bit Reserved.
Address Description
[13] This attribute is used during the RX programmable
divider ratio selection. Set to 1'b1 to obtain the full
rate of the divided clock. Set to 1'b0 to obtain the
half rate of the divided clock.
[12] This attribute is used during the RX programmable
divider ratio selection.
•
The attribute must be set to 1'b1 when the
desired divider value is either 16.5, 33, 66, or
132.
•
For all other divider values, this should be set to
1'b0.
[11] This attribute is used during the RX programmable
divider ratio selection.
•
The attribute must be set to 1'b0 when the
desired divider value is either 16.5, 33, 66, or
132.
•
For all other divider values, this should be set to
1'b1.
Chapter 4: Receiver
Description
This active-High port resets the dividers as
well as the RXPRGDIVRESETDONE
indicator. A reset must be performed
whenever the input clock source is
interrupted.
When the input clock is stable and reset is
performed, this active-High signal
indicates the reset is completed and the
output clock is stable.
RXPROGDIVCLK is the parallel clock output
from The RX programmable divider. This
clock is the recommended output to the
interconnect logic through BUFG_GT.
Description
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