Xilinx Virtex UltraScale+ FPGAs User Manual page 121

• Output voltage swing
• Jitter (deterministic, random, peak-to-peak)
• Rise and fall times
• Supply voltage and current
• Noise specification
• Duty cycle and duty-cycle tolerance
• Frequency stability
These characteristics are selection criteria when choosing an oscillator for a GTM transceiver
design. Figure 49
to-peak. This figure is provided to show the contrast to the differential clock input voltage swing
calculation shown in
data sheets (see
Figure 49:
+V
MGTREFCLKP
MGTREFCLKN
0
Figure 50 illustrates the differential clock input voltage swing, which is defined as MGTREFCLKP
- MGTREFCLKN.
Figure 50:
+V
0
–V
Figure 51 shows the rise and fall time convention of the reference clock.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
illustrates the convention for the single-ended clock input voltage swing, peak-
Figure 50, as used in the GTM transceiver portion of the UltraScale+ device
http:/ /www.xilinx.com/documentation).
Single-Ended Clock Input Voltage Swing, Peak-to-Peak
Differential Clock Input Voltage Swing, Peak-to-Peak
MGTREFCLKP – MGTREFCLKN
Chapter 5: Board Design Guidelines
Single-Ended Voltage
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